Efficient Implementations of AIMer Post-Quantum Signature Scheme for Low-End to High-End IoT Devices

Abstract

Post-Quantum Cryptography (PQC) is becoming increasingly critical for securing Internet of Things (IoT) applications against potential threats posed by quantum computers.
However, cryptographic schemes based on mathematically hard problems, such as lattice-based constructions, may face reduced security margins due to ongoing cryptanalytic advancements.
In IoT use cases requiring long-term deployment without guaranteed secure updates, symmetric-based signature schemes such as SPHINCS+, whose security relies solely on symmetric primitives, are considered robust alternatives.
Among these, AIMer, selected as a finalist in the Korean PQC competition, is emerging as a promising candidate.
This paper presents optimized software implementations of AIMer for various IoT platforms, ranging from low-end to high-end devices.
We propose memory-optimized and time–memory trade-off implementations for resource-constrained ARM Cortex-M4 devices, and SIMDaccelerated implementations for AArch64 and AVX2 architectures.
Furthermore, we conduct a comprehensive performance evaluation comparing our optimized implementations with other PQC signature schemes.
Our results show that AIMer achieves significantly smaller signature sizes and faster key generation and signing compared to SPHINCS+ across all security levels, making it a viable option for long-term IoT deployment.